This application relates in general to devices for testing the reliability of integrated circuits and in particular to a reliability qualification vehicle in the application specific integrated circuit (ASIC) industry to qualify a given technology, process and/or design system and packaging.
In the ASIC industry, while some ASIC manufacturers have manufactured integrated circuit chips designed for particular purposes of customers, the preferred approach by many ASIC manufacturers is to provide design tools which enable customers to design their own integrated circuit chips. Such an approach takes advantage of the intimate knowledge customers have of their requirement so that the chips designed would fit the customer's requirements more closely.
The design tools provided by VLSI Technology, Inc. of San Jose, Calif., for example, include cell libraries and place and route systems. The cell library would include building blocks such as flip-flops, registers, logic gates, multiplexers and counters. At least two place and route systems are offered for placing the cells in a semiconductor medium such as silicon and for interconnecting the portions of the cells according to customer design to form the desired integrated circuit chip. In one place and route system known as the standard-cell approach, the design of each cell in the library is optimized to reduce the areas of semiconductor medium required and to increase the speed and power performance. For this reason different cells in the library would usually differ in their diffusion, oxide and polysilicon layers. In the second approach known as gate-arrays, all the cells in the library will have the same oxide, diffusion, polysilicon and other layers, where the layers are substantially planar sheets uniformly distributed in the semiconductor medium. The cells in the library of the gate-array approach differ only in the way different portions of the layers are connected, usually through metal interconnects.
The gate-array approach is used usually when area economy in silicon, as well as power and heat dissipation considerations, are not paramount, such as when testing the internal consistency and feasibility of a particular crude design. At a preliminary stage of design, the primary concern is frequently merely the feasibility of the design. After the design proves to be practical, the design can be further improved in accordance with power and economy in area considerations. The gate-array approach is therefore frequently used in the preliminary design stage. After feasibility is proven, the standard-cell approach may be adopted for an improved design.
In both approaches, the design tools provided by ASIC manufacturers permit a customer to enter a schematic into a computer by entering the icons for the cells in a particular library. In both the standard-cell and the gate-array approaches, the computer would then fetch the particular layout of the cells so entered. After the customer or user enters the interconnections between the cells, a predetermined place and route system is then employed to connect the appropriate portions of the layers in the cells to be connected to provide a complete layout of all the different layers in the semiconductor medium and layout of the metal interconnections between the layers to yield a complete chip layout that accurately reflects customer design.
After an integrated circuit chip has been fabricated, it is necessary to test the reliability of the chip to assure that it is durable and would not fail during usage. To this date, no device has been expressly designed for qualifying the reliability of ASIC chips. Therefore, in order to test the reliability of a particular ASIC chip, the fabricated chip is tested in order to compile failure rate statistics. However, it is inherent in the nature of the ASIC design process that each chip designed using ASIC tools would differ from any other ASIC chip designed using the same ASIC tools. Hence every design would have to be qualified in manufacturing, which is impractical since this would entail thousands of separate qualifications. It is therefore desirable to provide a device expressly dedicated for testing and analysis, and for the compilation of failure rate statistics that will qualify substantially all devices manufactured using a particular ASIC design system, process, technology and packaging.